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MC74VHCT540A Octal Bus Buffer
Inverting
The MC74VHCT540A is an advanced high speed CMOS inverting octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHCT540A features inputs and outputs on opposite sides of the package and two AND-ed active-low output enables. When either OE1 or OE2 are high, the terminal outputs are in the high impedance state. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings. The VHCT540A input and output (when disabled) structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
Features
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20 1 SOIC DW SUFFIX CASE 751D VHCT540A AWLYYWW
20 1
TSSOP DT SUFFIX CASE 948E
VHCT 540A ALYW
* * * * * * * * * * * w
High Speed: tPD = 3.7 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4.0 A (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 1.2 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 124 FETs or 31 Equivalent Gates
These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at www.onsemi.com for specific Pb-free orderable part numbers, or contact your local ON Semiconductor sales office or representative.
20 1
SOIC EIAJ M SUFFIX CASE 967
74VHCT540 AWLYWW
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
FUNCTION TABLE
Inputs OE1 L L H X OE2 L L X H A L H X X Output Y H L Z Z
ORDERING INFORMATION
Device MC74VHCT540ADW MC74VHCT540ADT MC74VHCT540AM Package SOIC TSSOP SOIC Shipping 38 Units/Rail 75 Units/Rail 50 Units/Rail
(c) Semiconductor Components Industries, LLC, 2006
March, 2006 - Rev. 4
1
Publication Order Number: MC74VHCT540A/D
MC74VHCT540A
A1 A2 A3 DATA INPUTS A4 A5 A6 A7 A8 OUTPUT ENABLES OE1 OE2 2 3 4 5 6 7 8 9 1 19 18 17 16 15 14 13 12 11 Y1 Y2 OE1 Y3 Y4 Y5 Y6 Y7 Y8 INVERTING OUTPUTS A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
Figure 1. Logic Diagram
Figure 2. Pin Assignment
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1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 2. Derating - SOIC Packages: - 7.0 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS (Note 1)
SymbolIIIIIIIIIIIIIIIIIIIIIII Parameter VCC Vout Tstg IOK ICC Iout Vin PD IIK Storage Temperature Power Dissipation in Still Air (Note 2) SOIC Packages TSSOP Package DC Supply Current, VCC and GND Pins DC Output Current, per Pin Output Diode Current Input Diode Current DC Output Voltage DC Input Voltage DC Supply Voltage
DC ELECTRICAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
Symbol
Symbol
IOPD
ICCT
VOH
VOL
VIH
ICC
VIL
VCC
Vout
IIN
tr, tf
Vin
TA
Minimum High-Level Output Voltage VIN = VIH or VIL
Minimum High-Level Input Voltage
Output Leakage Current
Quiescent Supply Current
Maximum Quiescent Supply Current
Maximum Input Leakage Current
Maximum Low-Level Output Voltage VIN = VIH or VIL
Maximum Low-Level Input Voltage
Input Rise and Fall Time
Operating Temperature
DC Output Voltage
DC Input Voltage
DC Supply Voltage
Parameter
Vin = 5.5 V or GND
VIN = VIH or VIL IOL = 4.0 mA IOL = 8.0 mA
VOUT = 5.5 V
Input: VIN = 3.4 V
Vin = VCC or GND
VIN = VIH or VIL IOL = 50 A
VIN = VIH or VIL IOH = - 4.0 mA IOH = - 8.0 mA
VIN = VIH or VIL IOH = - 50 A
Test Conditions
VCC = 5.0 V 0.5 V
Outputs in 3-State High or Low State
Parameter
MC74VHCT540A
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0 to 5.5 VCC (V) 0.0 5.5 5.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 5.5 3.0 4.5 5.5 2.58 3.94 Min 2.9 4.4 1.2 2.0 2.0
3 TA = 25C Typ 0.0 0.0 3.0 4.5 1.35 0.1 0.36 0.36 0.53 0.8 0.8 Max 2.0 0.1 0.1 0.5 2.48 3.80 Min 2.9 4.4 1.2 2.0 2.0 TA 85C 1.50 1.0 0.44 0.44 0.53 0.8 0.8 Max 0.1 0.1 20 5.0 - 0.5 to VCC + 0.5 Min -55 - 65 to + 150 - 0.5 to + 7.0 - 0.5 to + 7.0 4.5 0 0 0 0 Value 75 25 20 - 20 500 450 2.34 3.66 Min 2.9 4.4 1.2 2.0 2.0 TA 125C MaxIII Unit 5.5 VCC 125 5.5 5.5 20 1.65 1.0 0.52 0.52 0.53 0.8 0.8 Max 0.1 0.1 40 10 ns/V Unit mW mA mA mA mA _C _C Unit V V V V V V mA A A V V V V A
MC74VHCT540A
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
TA = 25C Typ 4.8 7.3 3.7 5.2 6.8 9.3 4.7 6.2 TA = - 40 to 85C TA 125C Symbol tPLH, tPHL Parameter Test Conditions Min Max Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max Min Max Unit ns Maximum Propagation Delay, A to Y (Figures 1 and 3) VCC = 3.3 0.3 V CL = 15 pF CL = 50 pF VCC = 5.0 0.5 V CL = 15 pF CL = 50 pF VCC = 3.3 0.3 V CL = 15 pF CL = 50 pF RL = 1.0 k VCC = 5.0 0.5 V CL = 15 pF RL = 1.0 k CL = 50 pF VCC = 3.3 0.3 V CL = 50 pF RL = 1.0 k VCC = 5.0 0.5 V CL = 50 pF RL = 1.0 k VCC = 3.3 0.3 V CL = 50 pF (Note 3) VCC = 5.0 0.5 V CL = 50 pF (Note 3) 7.0 10.5 5.0 7.0 8.5 12.0 6.0 8.0 10.5 14.0 8.0 10.0 tPZL, tPZH Output Enable TIme, OEn to Y (Figures 2 and 4) 10.5 14.0 7.2 9.2 12.5 16.0 15.0 19.0 10.5 13.0 20.0 11.5 2.0 1.5 10 ns 8.5 10.5 tPLZ, tPHZ Output Disable Time, OEn to Y (Figures 2 and 4) 11.2 6.0 15.4 8.8 1.5 1.0 10 17.5 10.0 1.5 1.0 10 ns tOSLH, tOSHL Output to Output Skew ns ns Cin Maximum Input Capacitance 4.0 6.0 pF pF Cout Maximum Three-State Output Capacitance (Output in High Impedance State) Typical @ 25C, VCC = 5.0V 17 CPD Power Dissipation Capacitance (Note 4) pF 3. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. 4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Parameter Typ 0.9 - 0.9 Max 1.2 -1.2 3.5 1.5 Unit V V V V
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4
MC74VHCT540A
3.0V 3.0V A tPH
L
OE1 or OE2
1.5V tPZL tPLZ
50% GND HIGH IMPEDANCE VOL +0.3V tPZH tPHZ VOH -0.3V HIGH IMPEDANCE
1.5V tPLH 1.5V VOL Y GND VOH Y
1.5V
Y
1.5V
Figure 3. Switching Waveform
Figure 4. Switching Waveform
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST OUTPUT
TEST POINT 1k CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
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5
MC74VHCT540A
PACKAGE DIMENSIONS
SOIC DW SUFFIX CASE 751D-05 ISSUE F
D A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
TSSOP DT SUFFIX CASE 948E-02 ISSUE A
20X
K REF
M
L
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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6
IIII IIII IIII
SECTION N-N 0.25 (0.010) M DETAIL E -W-
L/2
20
11
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
MC74VHCT540A
PACKAGE DIMENSIONS
SOIC EIAJ M SUFFIX CASE 967-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e A VIEW P
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74VHCT540A/D

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